Image sensor applied with device isolation technique for reducing dark signals and fabrication method thereof

ABSTRACT

The present invention relates to an image sensor applied with a device isolation technique for reducing dark signals and a fabrication method thereof. The image sensor includes: a logic unit; and a light collection unit in which a plurality of photodiodes is formed, wherein the photodiodes are isolated from each other by a field ion-implantation region formed under a surface of a substrate and an insulation layer formed on the surface of the substrate.

FIELD OF THE INVENTION

The present invention relates to an image sensor; and, moreparticularly, to an image sensor applied with a device isolationtechnique for reducing dark signals and a fabrication method thereof.

DESCRIPTION OF RELATED ARTS

As known, a device isolation technology has been employed toelectrically isolate individual devices such as a transistor and acapacitor during fabrication of a semiconductor integration circuit.Among various techniques of the device isolation technology, a localoxidation of silicon (LOCOS) technique and a shallow trench isolation(STI) technique are commonly adopted.

The LOCOS technique is a method of forming a nitride layer-based maskpattern on an active region of a silicon substrate and thermallyoxidating the silicon substrate with use of the mask pattern as a mask.However, the LOCOS technique has disadvantages that an oxide layer isformed in a wide area and a bird's beak phenomenon occurs at aninterfacial surface between the oxide layer and the silicon substrate.Thus, it is limited to apply the LOCOS technique to highly integrateddevices. As a result of this limitation, the STI technique is morewidely employed in highly integrated devices since the STI techniqueforms a device isolation region by forming a shallow trench in asubstrate and then burying an oxide layer into the trench.

Meanwhile, an image sensor is a semiconductor device that converts anoptical image into an electric signal. Among various types of the imagesensor, a charge coupled device (CCD) and a complementary metal oxidesemiconductor (CMOS) image sensor are widely distributed. Such an imagesensor has photodiodes within a unit pixel, and the photodiodes formedin neighboring unit pixels need to be individually isolated through theuse of a device isolation layer.

The device isolation layer formed by a LOCOS technique or a STItechnique for isolating each photodiode is impaired by numerous defectscreated by stress generated at a boundary region between a field regionand an active region. These defects severely affect a darkcharacteristic, which is one of the most important characteristics of animage sensor. Therefore, it is strongly necessary to develop aneffective device isolation technology applicable to a specificcharacteristic of an image sensor.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide an imagesensor applied with a device isolation technique for reducing darksignals and a fabrication method thereof.

In accordance with an aspect of the present invention, there is providedan image sensor, including: a logic unit; and a light collection unit inwhich a plurality of photodiodes is formed, wherein the photodiodes areisolated from each other by a field ion-implantation region formed undera surface of a substrate and an insulation layer formed on the surfaceof the substrate.

In accordance with another aspect of the present invention, there isalso provided a complementary metal oxide semiconductor (CMOS) imagesensor, including: a logic unit; and a pixel array unit in which aplurality of photodiodes is formed, wherein the photodiodes are isolatedfrom each other by a field ion-implantation region formed under asurface of a substrate and an insulation layer formed on the surface ofthe substrate.

In accordance with still another aspect of the present invention, thereis also provided a method for forming a device isolation structure of animage sensor including a light collection unit and a logic unit,including the steps of: forming an insulation layer pattern on asubstrate in a field region of the light collection unit; forming aninsulation layer for device isolation in a field region of the logicunit by performing one of a LOCOS technique and a STI technique; andforming a field ion-implantation region under a surface of the substratein the field region of the light collection unit.

BRIEF DESCRIPTION OF THE DRAWING(S)

The above and other objects and features of the present invention willbecome apparent from the following description of the preferredembodiments given in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a cross-sectional view showing a device isolation structure inan image sensor for reducing dark signals in accordance with a firstpreferred embodiment of the present invention;

FIG. 2 is a cross-sectional view showing a complementary semiconductormetal oxide semiconductor (CMOS) image sensor having a device isolationstructure in accordance with a preferred embodiment of the presentinvention; and

FIGS. 3A to 3F are cross-sectional views illustrating a method forforming a device isolation structure in an image sensor in accordancewith the preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a preferred embodiment of the present invention will bedescribed in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view showing a device isolation structure inan image sensor in accordance with a preferred embodiment of the presentinvention.

As shown, the image sensor is divided into a light collection unit A inwhich photodiodes are formed and a logic unit B in which typicalcomplementary metal oxide semiconductor (CMOS) devices are formed. Inthe light collection unit A, there is a plurality of photodiodes 10A and10B which generate photo-charges after collecting lights. Herein, thereference numbers 10A and 10B will be referred to as a first and asecond photodiodes, respectively. A field ion-implantation region 20 isformed beneath a predetermined surface of a silicon substrate 100disposed between the first photodiode 10A and the second photodiode 10B.An insulation layer 30 is formed on the predetermined surface of thesilicon substrate 100. The field ion-implantation region 20 and theinsulation layer 30 isolate the adjacently allocated first and secondphotodiodes 10A and 10B. If the silicon substrate 100 is a firstconductive type, the first and the second photodiodes 10A and 10B are asecond conductive type and the field ion-implantation region 20 is thefirst conductive type. Also, in the logic unit B, a conventional localoxidation of silicon (LOCOS) technique and/or a shallow trench isolation(STI) technique is performed to form an insulation layer 60, which is adevice isolation layer.

As described above, in order to reduce dark signals of an image sensor,the light collection unit A is applied with a specialized deviceisolation technique, while the logic unit B is applied with theconventional LOCOS and/or STI technique. More specifically, the LOCOStechnique and the STI technique are compulsorily accompanied with athermal oxidation process. Thus, defects are created by stress generatedat an interfacial surface between a field region and a device isolationregion, thereby resulting in a problem of dark signals. However, in thispreferred embodiment, generation of dark signals is reduced since thedevice isolation layer is formed by performing the ion-implantationprocess which does not require the thermal oxidation process anddepositing the insulation layer.

FIG. 2 is a cross-sectional view showing a CMOS image sensor with adevice isolation structure in accordance with the preferred embodimentof the present invention.

As shown, the CMOS image sensor is divided into a pixel array unit C inwhich photodiodes are formed and a logic unit D in which typical CMOSdevices are formed. In the pixel array unit C, a photodiode 10 forgenerating photo-charges after collecting lights and a transfer gate Txfor transferring the photo-charges generated from the photodiode 10 to asensing node 40 are formed. Also, a field ion-implantation region 20 andan insulation layer 30 isolate the devices in the pixel array unit C,while a device isolation layer 60A formed in the logic unit D byemploying a STI technique or a LOCOS technique isolates the typical CMOSdevices from each other. Hence, it is possible to reduce the number ofdefects generated at an interface 200 between a field region and anactive region and further to reduce the number of dark signals.

Meanwhile, in consideration of process specifications such asion-implantation energy, the insulation layer 30 for device isolationshould have a predetermined thickness. That is, ion-implantation energyspecified in a currently applied image sensor process is determinedunder consideration of a thickness of a device isolation layer formed bya LOCOS technique. Thus, the insulation layer 30 should be formed with apredetermined thickness identical to the thickness of a field oxidelayer growing towards an upper surface of a silicon substrate throughthe use of a LOCOS technique in order not to change subsequent processconditions such as ion-implantation energy. Also, when the abovespecific device isolation structure is formed on the basis of thepreferred embodiment, it is necessary to minimize changes in currentlyapplied process conditions. Detailed descriptions on a method forforming the specific device isolation structure without changing thecurrently applied process conditions will be provided in the following.

FIGS. 3A to 3F are cross-sectional views illustrating a method forforming the device isolation structure in an image sensor in accordancewith the preferred embodiment of the present invention.

Referring to FIG. 3A, an oxide layer 302 and a nitride layer 303 aredeposited on a silicon substrate 301. Herein, the oxide layer 302 isdeposited to a thickness ranging from about 2000 Å to about 2500 Å, andthe nitride layer 303 is deposited to a thickness ranging from about1000 Å to about 1500 Å. A first device isolating mask pattern 304 foropening an active region of a light collection unit and an entire regionof a logic unit is formed on the above resulting structure.

Specifically, the nitride layer 303 is a layer used to make sidewalls ofa subsequently formed oxide layer pattern inclined. Also, the oxidelayer 302 is grown through a thermal oxidation process, which makesimpurities existing within the silicon substrate 301 diffusedexternally. As a result of this external diffusion, it is possible toobtain a gettering effect. Also, the oxide layer 302, which will be usedas the insulation layer 30 for device isolation as depicted in FIG. 1,should be sufficiently thick in consideration of subsequent processes,e.g., an ion-implantation process. For instance, since a typicalthickness of a field oxide layer grown towards an upper surface of asilicon substrate by employing a LOCOS technique is about 2200 Å, it isrequired to form the oxide layer 302 at least with such thickness. Thefirst device isolating mask pattern 304 is a photoresist PR formed by aconventional photolithography process.

FIGS. 3B and 3C are cross-sectional views showing an etched state of thenitride layer 303 and the oxide layer 302 in the opened active region byusing the first device isolating mask pattern 304. Particularly, FIG. 3Bis a cross-sectional view showing the etched state of the nitride layer303 and the oxide layer 302 after a dry etching process. On the otherhand, FIG. 3C is a cross-sectional view showing the etched state of thenitride layer 303 and the oxide layer 302 after a wet etching process.

Preferably, the dry etching process is performed such that a lateralprofile of the oxide layer 302 is patterned to have an inclination in anangle of about 60°, which is denoted as the reference symbol B in FIG.3B. The reason for this inclination is to prevent generation of remnantsin a conductive layer, e.g., a polysilicon layer for use in a gateelectrode. Also, it is preferable to form an undercut, denoted as thereference symbol A, at a bottom portion of each sidewall of the nitridelayer 303 patterned by the dry etching process. The reason for formingthe undercut is to round an upper part of the oxide layer 302 during thesubsequent wet etching process. In addition, during the dry etchingprocess, the oxide layer 302 is made to remain in a thickness rangingfrom about 600 Å to about 700 Å in order to prevent the siliconsubstrate 301 from being damaged by a plasma used during the dry etchingprocess. This remaining oxide layer 302 is denoted as the referencesymbol C in FIG. 3B.

With reference to FIG. 3D, the first device isolating mask pattern 304and the nitride layer 303 are removed. Then, a pad oxide layer 305 and apad nitride layer 306 are deposited for device isolation in the logicunit. At this time, the pad oxide layer 305 has a thickness ranging fromabout 100 Å to about 200 Å, while the pad nitride layer 306 has athickness ranging from about 1000 Å to about 1500 Å. Thereafter, asecond device isolating mask pattern 307 opening a field region in thelogic unit is formed on the above resulting structure.

Referring to FIG. 3E, the second device isolating mask pattern 307 isremoved, and a field insulation layer 308 is grown in the logic unit byperforming a thermal process. The pad nitride layer 306 and the padoxide layer 305 are removed thereafter.

FIGS. 3D and 3E disclose the steps of forming the device isolation layerin the field region of the logic unit by employing the conventionalLOCOS technique. However, in addition to the LOCOS technique, it isstill possible to form the device isolation layer in the logic unit by aconventional STI technique.

Referring to FIG. 3F, a selective ion-implantation process is performedonly to the field region in which the oxide layer 302 remains in thelight collection unit. From the selective ion-implantation process, afield ion-implantation region 309 is formed under a surface of thesilicon substrate 301 disposed below the oxide layer 302 in the lightcollection unit.

On the basis of the preferred embodiment of the present invention, thelight collection unit is applied with a specialized device isolationtechnique for forming the field ion-implantation region and the oxidelayer. On the contrary, the logic unit is applied with the conventionalLOCOS and/or STI technique. As a result, it is possible to preventdefect generations caused by stress in the light collection unit,thereby reducing dark signals. Therefore, it is further possible toimprove a low light level characteristic of an image sensor and increaseyields. Moreover, since the device isolation structure can be obtainedwith minimum changes in the conventionally employed processes, there isan additional effect of shortening periods and reducing costs fordevelopment and mass-production of image sensors.

The present application contains subject matter related to the Koreanpatent application No. KR 2003-0091843, filed in the Korean PatentOffice on Dec. 16, 2003, the entire contents of which being incorporatedherein by reference.

While the present invention has been described with respect to certainpreferred embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the scope of the invention as defined in the following claims.

1. An image sensor, comprising: a logic unit; and a light collectionunit in which a plurality of photodiodes is formed, wherein thephotodiodes are isolated from each other by a field ion-implantationregion formed under a surface of a substrate and an insulation layerformed on the surface of the substrate.
 2. The image sensor as recitedin claim 1, wherein the substrate and the field ion-implantation regionare formed of a first conductive type and the photodiode is formed of asecond conductive type.
 3. The image sensor as recited in claim 1,wherein the insulation layer is an oxide layer grown by a thermalprocess.
 4. The image sensor as recited in claim 1, wherein the logicunit includes an insulation layer for device isolation formed by a localoxidation of silicon (LOCOS) technique and a shallow trench isolation(STI) technique.
 5. A complementary metal oxide semiconductor (CMOS)image sensor, comprising: a logic unit; and a pixel array unit in whicha plurality of photodiodes is formed, wherein the photodiodes areisolated from each other by a field ion-implantation region formed undera surface of a substrate and an insulation layer formed on the surfaceof the substrate.
 6. The CMOS image sensor as recited in claim 5,wherein the substrate and the field ion-implantation region are formedof a first conductive type and the photodiode is formed of a secondconductive type.
 7. The CMOS image sensor as recited in claim 5, whereinthe logic unit includes an insulation layer for device isolation formedby one of a LOCOS technique and a STI technique.
 8. The CMOS imagesensor as recited in claim 5, wherein the insulation layer is an oxidelayer grown by a thermal process.
 9. The CMOS image sensor as recited inclaim 5, wherein the insulation layer is formed with a predeterminedthickness in consideration of ion-implantation energy used in asubsequent ion-implantation process.
 10. A method for forming a deviceisolation structure in an image sensor including a light collection unitand a logic unit, comprising the steps of: forming an insulation layerpattern on a substrate in a field region of the light collection unit;forming an insulation layer for device isolation in a field region ofthe logic unit by performing one of a LOCOS technique and a STItechnique; and forming a field ion-implantation region under a surfaceof the substrate in the field region of the light collection unit. 11.The method as recited in claim 10, wherein the insulation layer patternis formed in a manner to have inclined sidewalls.
 12. The method asrecited in claim 10, wherein the step of forming the insulation layerpattern includes the steps of: stacking an oxide layer and a nitridelayer on a substrate; forming a mask pattern on the nitride layer, themask pattern opening an active region of the light collection unit;performing a dry etching process and a subsequent wet etching process tothe nitride layer and the oxide layer by using the mask pattern as anetch mask; and removing the mask pattern and the nitride layer.
 13. Themethod as recited in claim 10, wherein an undercut is formed at a bottomportion of each sidewall of the nitride layer patterned by the dryetching process.
 14. The method as recited in claim 10, wherein theoxide layer is made to remain in a thickness ranging from about 600 Å toabout 700 Å during the dry etching process.
 15. The method as recited inclaim 12, wherein the oxide layer is grown by a thermal process.